The generation of a chip includes, manufacturing and three links. The design of the chip is at the forefront of the germination of the chip.
The chip design industry needs to work closely with the back-end wafer manufacturing, packaging and testing links of the industry chain. It is not only necessary to consider whether the process can achieve the corresponding circuit design at the design stage, but also need to integrate the resources of the industry chain to ensure the timely supply of chip products. Therefore, it is also a test of the ability of enterprises to complete this series of production. Jinyu Semiconductor can provide customers with one-stop application solutions and on-site technical support services.
The chip contains thousands of PN junctions, capacitors, resistors, wires, etc., so the chip design is a typical technology intensive industry, which greatly tests the technical ability of engineers, because the design level of engineers largely determines the performance, function, cost and other core factors of the chip.
At the beginning of chip design, it is necessary to define the purpose, specification and performance of the chip, so that engineers can divide the internal specification of the chip according to the characteristics of the chip, plan the functional demand space of each part, establish the connection method between different units, and determine the overall direction of the design. This part does not seem to have much technical content, but it plays a vital role in the later design. If the regional division is not enough, the realization of the functions in this area cannot be completed, which will lead to the overthrow of all previous work.
Then, based on the early specification definition, the chip architecture, business module, power supply and other system level designs are defined, such as CPU, GPU, NPU, RAM, connection, interface, etc. The chip design needs to comprehensively consider the system interaction, function, cost, power consumption, performance, security, maintainability and measurability of the chip.
Next, according to the scheme determined by the system design, the designer carries out specific circuit design for each module, and uses a special hardware description language (Verilog or VHDL) to describe the specific circuit implementation at the RTL (Register Transfer Level) level. After the code is generated, it is necessary to repeatedly determine whether the logic gate design diagram conforms to the specification and modify it in strict accordance with the established specifications and standards until the function is correct.
Then, using logic synthesis tools, RTL level codes written in hardware description language are converted into gate level netlists to ensure that the circuit meets the standard in area, timing and other target parameters. After the completion of logic synthesis, it is necessary to conduct static timing analysis, apply a specific timing model, and analyze whether it violates the timing limit given by the designer for a specific circuit. The whole design process is an iterative process. If any step fails to meet the requirements, the previous steps need to be repeated, or even the RTL code needs to be redesigned.
Finally, according to the silicon area of the size given by the NetList, the circuit is laid out and wound, and then the physical layout of the wiring is verified in terms of function and timing. This is also an iterative process. If the verification does not meet the requirements, the previous steps need to be repeated, and finally the GDS (Geometry Data Standard) layout for chip production is generated.
It is worth noting that many variables need to be considered in chip design, such as signal interference, heat distribution, etc. The physical characteristics of the chip, such as magnetic field and signal interference, are very different under different manufacturing processes, so we can only rely on EDA tools to design step by step, simulate step by step, and constantly make choices.
After each simulation, if the effect is not ideal, it needs to be redesigned. Through inspection, simulation, prototype platform and other means, it is not a process after the design is completed, but a repetitive behavior throughout each link of the design. This is to discover the functional errors of the system software and hardware in advance, further optimize the performance and power consumption, and make the design accurate, reliable, and in line with the originally planned chip specifications. This is a great test of the team's wisdom, energy, and patience.
